Stuck? Each stage below says what the game asks for and why it is hard. Hints are folded, weakest first. Open only as many as you need. None of them hands you a finished circuit.
Every time you change the circuit, the analyzer runs it from the seed and grades a sample. Quality is every test's score multiplied together, so one bad test sinks the lot. Start with the lowest score and ignore the rest until it's fixed.
The sample bitmap is often quicker than the numbers. These come from real circuits:
Experiments are cheap. The analyzer updates as you edit, Undo puts anything back, and Designs A–D in Production hold four circuits side by side. Save one before you start tearing it apart.
Goal: earn 120 b and buy Gate slot 4.
With three XOR and SHIFT gates, no 8-bit circuit loops for long: the best manage about a dozen ticks. That is expected. Anything that keeps moving earns a trickle, and the fourth slot is where the real game starts.
A circuit earns as long as it keeps changing. Watch for "Fell into zero" in the analyzer: an all-zero register stays zero under XOR and SHIFT forever.
Shifted copies going both ways mix better than shifts in one direction only.
Prove: an 8-bit circuit whose loop lasts 200 ticks or more. This opens 16-bit registers.
An 8-bit register has 256 values, and zero is a trap, so 255 ticks is the ceiling. Most circuits never get near it, because they merge states: two different values lead to the same next value. Each merge shrinks the set of values the register can still reach, until it is caught in a small loop or sinks to zero.
Look for steps that can be undone: if you can always work out the previous value from the current one, nothing merges. A SHIFT on its own can't be undone, because the bits it pushes off the end are gone.
XOR-ing a value with a shifted copy of itself can always be undone. XOR-ing two different shifted copies often can't, because the original value isn't in the result any more.
One undoable step on its own still loops quickly. Chain two of them, shifting in opposite directions, and try different amounts. Watch the Period line in the analyzer.
Prove: 90% quality at Grade I. This opens Grade II and a faster clock.
Grade I reads 2,048 bits, which is 256 ticks at 8 bits. A loop shorter than the sample costs you in proportion, so 90% needs a loop of about 230 ticks or more, close to the 255 ceiling, with every other test still clean. At 8 bits there's little room for both.
Look at the lowest score. If it's Period, the loop is still a little short. If it's Autocorrelation, read which distance has the tall bar: that echo is what's left to break, and it often moves or vanishes when you change a single amount.
A third undoable step makes it much easier to reach the full 255 without leftover echoes. You'll need two more gate slots for it.
You don't have to win this at 8 bits. Once 16-bit registers are yours, ROTATE keeps every bit, and with 65,536 values to wander through, small circuits go a lot further.
Prove: 90% at Grade II (opens 32-bit registers, a second register and a faster clock), then 95% at Grade II with 32-bit registers (opens Grade III).
Grade II reads 16,384 bits. At 8 bits per tick that's 2,048 ticks, eight times the longest possible 8-bit loop, so no 8-bit circuit can pass, however good. It also adds the pattern-pair test.
What worked at 8 bits often works wider, but the right amounts change with the width. An amount that is small compared to the register mixes slowly.
When a design almost passes, change one thing at a time: one amount, or one direction. Save the near misses to Designs and compare them.
Small circuits can pass here. If your Grade II design uses lots of gates, try building a new one from just a rotation, a shift and an XOR.
Prove: 50% quality at Grade III. This opens the fastest clocks.
Every circuit made only of XOR, SHIFT, ROTATE and NOT is linear: each output bit is an XOR of seed bits. The linear-complexity test (Berlekamp–Massey) finds a short XOR recipe that predicts such bits, so it fails every linear circuit, however long the loop and however clean the other tests.
AND and OR are not linear. But they throw information away: AND of two bits is 1 only a quarter of the time. Feed one straight back into the register and states start merging again, which is Stage 2's problem all over.
Keep a long, undoable linear loop as the engine. Then put AND or OR somewhere it can't drain that loop.
A single AND on the output is not enough. The test needs the nonlinearity to build up over time, and the easiest place for that is inside a register.
The second register is a safe place for it. Let R0 run on its own. Stir R1 with R0 through an AND or an OR, and XOR the result back into R1. Then think about what OUTPUT should show.
clock ÷ gates × bits per tick × quality × the grade's pay = bits per second
A circuit like this never creates randomness. It stretches its seed into a long, scrambled sequence. Passing the tests is not proof of randomness, and it says nothing about whether the output is safe for passwords or keys.